1. Technical Field
The present invention relates to a refresh control circuit in a semiconductor memory apparatus and a method of controlling a period of a refresh signal using the same, and more particularly, to a refresh control circuit in a semiconductor memory apparatus and a method of controlling a period of a refresh signal using the same that controls the period of a refresh signal according to temperature.
2. Related Art
In general, a memory cell of a DRAM (Dynamic Random Access Memory) may include one transistor and one capacitor, and the data stored in the capacitor is volatile. Therefore, in order to prevent data being lost due to generation of a leakage current from semiconductor memory cells, a refresh operation is required such that data is periodically rewritten in each of the cells so as to maintain the data that each of the cells stores. The refresh operation is performed when a refresh signal is enabled. The refresh signal is a pulse signal that has a predetermined period.
In general, the threshold voltage of transistors in a semiconductor memory apparatus increases at low temperatures and decreases at high temperatures. In addition to the transistors, the operating characteristics of various other elements in a semiconductor integrated circuit are distorted according to a temperature change. Therefore, it is possible to prevent a reduction in operating efficiency when the semiconductor memory apparatus can adjust to temperature changes. Also, the refresh operation needs to be performed according to temperature changes. Therefore, a circuit that sets the period of a refresh signal according to a temperature condition is used.
FIG. 1 shows the structure of a refresh control circuit for a semiconductor memory apparatus according to the related art. In FIG. 1, digital codes that are used to control the refresh period by detecting temperature have 5 bits.
As shown in FIG. 1, the refresh control circuit includes a temperature detecting unit 10 that detects the temperature according to whether a detection enable signal den is enabled or not, and generates a temperature detecting voltage Vtmp, a digital converting unit 20 that converts the temperature detecting voltage Vtmp into five bits of digital code t1 to t5, a refresh signal generating unit 30 that generates a refresh signal rfsh that has a period corresponding to the input of the five bits of digital code t1 to t5, and a reference signal rfc, and a detection instructing unit 40 that generates the detection enable signal den according to the input of the reference signal rfc.
The reference signal rfc generated by the refresh signal generating unit 30 is a signal that is enabled for every predetermined period to operate the detection instructing unit 40 regardless of the logic values of the inputted five bits of digital code t1 to t5. The detection instructing unit 40 generates the detection enable signal den according to the input of the reference signal rfc. Here, the detection enable signal den is generated such that it also has a predetermined period. Therefore, the temperature detecting unit 10 detects the temperature every predetermined period.
The temperature detecting voltage Vtmp output from the temperature detecting unit 10 is a voltage whose potential level changes according to a change in temperature. The digital converting unit 20 generates the five bits of digital code t1 to t5 that correspond to the level of the temperature detecting voltage Vtmp. The refresh signal generating unit 30 generates the refresh signal rfsh with a period corresponding to the logic values of the five bits of digital code t1 to t5.
FIG. 2 shows the detailed structure of the digital converting unit shown in FIG. 1.
The digital converting unit 20 includes a comparator CMP that compares the temperature detecting voltage Vtmp with a feedback signal fdb and outputs an up/down indication signal udp, a counter CNT that generates the five bits of digital code t1 to t5 according to the up/down indication signal udp and transmits the five bits of digital code t1 to t5 to the refresh signal generating unit 30 and a DA converter DAC, and the DA converter DAC that converts the five bits of digital code t1 to t5 into the analog feedback signal fdb.
The up/down indication signal upd that is output from the comparator CMP has a potential of either a high level or a low level according to whether or not the potential level of the temperature detecting voltage Vtmp exceeds the potential level of the feedback signal fdb. Then, the counter CNT increases or decreases the logic values of the five bits of digital code t1 to t5 according to the potential level of the up/down indication signal udp. The five bits of digital code t1 to t5 that have arbitrary logic values according to such an operation are then transmitted to the refresh signal generating unit 30 so as to determine the period of the refresh signal rfsh. The DA converter DAC converts the five bits of digital code t1 to t5 into an analog signal again. The feedback signal fdb generated at this time is transmitted to the comparator CMP and compared with the temperature detecting voltage Vtmp.
However the digital converting unit 20 has a feedback structure. Therefore, when an error, such as a gain error or the like, occurs in a component such as the comparator CMP or the DA converter DAC, the error may be increasingly amplified through the feedback structure. Due to the small size of the various devices used in the semiconductor memory apparatus, high precision is required in manufacturing processes, which may also cause defects. In addition, each of the devices may malfunction because of a side effect, such as noise, caused by the high integration. For the above-described reasons, an error may occur in the comparator CMP and the DA converter DAC. As a result, the feedback structure of the digital converting unit 20 malfunctions, which increases the number of errors. The malfunction of the digital converting unit 20 affects the overall refresh control operation of the semiconductor memory apparatus. However, in the prior art, an apparatus and a method that can easily prevent the malfunction do not exist.